Domain
Design Verification
DV engineers build UVM testbenches, write constrained random tests, define coverage models and drive sign-off with formal and assertion based methods.
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Daily work
- Develop UVM agents, sequences and scoreboards
- Run regressions and triage failures
- Close functional and code coverage
- Write assertions and review specs
Required skills
- SystemVerilog & UVM
- Constrained random testing
- SVA assertions
- Python/Perl scripting
Career roadmap
- OOP with SystemVerilog
- Build a class-based testbench
- Learn UVM base classes and phases
- Coverage closure & regression management
Future scope
Verification consumes ~60-70% of chip effort — the largest and steadiest hiring pool in India.
Learning path for Design Verification
Beginner roadmap
- Month 1: SV OOP
- Month 2: layered testbench
- Month 3: UVM components
- Month 4: coverage + formal basics
Recommended books
- SystemVerilog for Verification — Chris Spear
- The UVM Primer — Ray Salemi
Practice projects
- UVM testbench for an APB slave
- Coverage-driven FIFO verification
- cocotb tests for a RISC-V core