Domain
Physical Design
Physical design engineers handle floorplanning, placement, CTS, routing, and signoff for timing, power, IR drop and physical verification.
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Daily work
- Run floorplan, placement and CTS iterations
- Fix timing, congestion and DRC violations
- Analyse IR drop and EM reports
- Deliver blocks for tapeout signoff
Required skills
- Innovus/ICC2
- STA fundamentals
- TCL scripting
- Physical verification (DRC/LVS)
Career roadmap
- Learn CMOS and standard cells
- Understand STA deeply
- Practice a full RTL-to-GDS flow
- Signoff tools and ECO handling
Future scope
PD hiring is booming with new India design centres and advanced node work at 5nm/3nm.
Learning path for Physical Design
Beginner roadmap
- Basics of CMOS
- STA
- PnR flow
- Signoff & ECO
Recommended books
- Static Timing Analysis for Nanometer Designs — Bhasker & Chadha
- VLSI Physical Design — Kahng et al.
Practice projects
- RTL2GDS of a picorv32 core with OpenLane
- Custom floorplan experiments
- CTS skew optimisation study