Domain
DFT (Design for Test)
DFT engineers insert test structures, generate ATPG patterns and ensure high defect coverage while managing test time and cost.
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Daily work
- Scan insertion and stitching
- ATPG pattern generation
- MBIST/BSCAN integration
- Coverage and test-time analysis
Required skills
- Scan/ATPG (Tessent, TetraMAX)
- JTAG 1149.1
- Fault models
- TCL/Python
Career roadmap
- Digital basics
- Fault models & scan
- ATPG tools
- Silicon bring-up interaction
Future scope
Chiplets and automotive safety push DFT demand higher every year.
Learning path for DFT (Design for Test)
Beginner roadmap
- Fault modelling
- Scan architecture
- ATPG flows
- Memory BIST
Recommended books
- Essentials of Electronic Testing — Bushnell & Agrawal
Practice projects
- Insert scan chains into an open core
- Generate ATPG patterns and measure coverage